DESIGN AND EVALUATION OF FIELD PROGRAMMABLE GATE ARRAY (FPGA) BASED RIEMANN SUMMATION DEFINITE INTEGRAL EQUATION SOLVER.
Publication Date : 26/04/2022
The attempts made to implement definite integrals in hardware has largely focused on microcontrollers which are devices which operate sequentially. Recent attention has been focused on the idea of implementing definite integral systems on field programmable gate arrays (FPGAs). It is in this regard that this research was envisioned, i.e. to develop a definite integral equation solver based on the Riemann summation with an FPGA as the target device. To achieve this objective, an arithmetic logic unit (ALU) capable of performing integer addition, subtraction, multiplication, and division was designed and developed using VHDL (VHSIC Hardware Description Language). The ALU was used in executing the algorithm of the Riemann Summation which effectively performs the definite integral operations. A definite integral equation was successfully solved using the developed solver. The results obtained were accurate as indicated in the output figures of the solver, which tally with the manually generated values in the research. The research is limited to the successful development and implementation of the definite integral solver. The performance analysis and comparison with similar works, error analysis, and dynamic and static power analysis to determine the efficiency of power consumption and values comparison with those generated by an equivalent simulink model will form the basis of a another research work.
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